In data processing, there are various devices employed for the manipulation of numbers and data. One of these devices is a “floating point unit” (FPU), which is typically used to add and multiply floating point numbers to one another. There are complexities, however, to designing and operating an FPU. One such problem concerns the alignment of numbers. For numbers to be added, they should be expressed in a form that is easy to add to one another, with additional exponent information. For instance, if the number 11100011 with exponent value 3 were to be added to 11000111 with an exponent value of −2, the two numbers would be added as follows. The first number used is extended on the least significant digit by 5 zeroes before it can be added to the second number.
In FPUs, featuring a fused-multiply-add instruction, three floating point operands A, B and C are combined to one result, “R” by R=A*B+C. Other, operations, such as multiplication or addition, are obtained by forcing C=0 or A=1, respectively. The floating point operands are given in IEEE format. In this format, every number has a sign bit, an exponent and a fraction, which shall be designated sa, ea, fa, for operand A, respectively. Sb, eb, bf, sc, ec and fc for operands for B and C, respectively. The value of A is given by ((−1)sa*2ea*fa), for example. The product of A and B is denoted P, which consists of sp, ep, and fp.
One of the central components of such FPU designs is the alignment shifter, which aligns the fraction of operand “c” to the fraction of the intermediate product “P” with respect to the exponents of C and P. This alignment shift yields an alignment of the binary points of C and P before these two numbers are added. For this alignment, the fraction fc is shifted. A shift amount “sha” is computed as sha=ea+eb−ec+constant. The constant arises as a matter of system design. If the shift amount is in a given range, the alignment is performed by an actual shifter. If the shift amount is outside of a given range, these other cases are handled as “special” cases, that is, the shift amount (sha) underflow and overflow, respectively.
Generally, in a conventional multiply-add FPU, there are three exponent numbers that are added. These three numbers generate in turn, two numbers, which are in turn added by a 2:1 adder, thereby producing a shift amount. In conventional technology, the shift amount (“sha”) is sent to decoders, such as a 1b decoder, a 2b decoder, and a 3b decoder. These decoders then determine the number of bits by which the fractional part of the addend, the fraction fc, is to be shifted. Typically, the shift is broken up into several shift stages.
However, there are problems associated with this technology. Specifically, the shift amount adders and decoders are both on the timing-critical path of the aligner.
Therefore, there is a need for an aligner that addresses at least some of the issues associated with conventional aligners.